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Three Things to Improve High-Speed PCB Signoff, Part 2

09/27/2023 | Brad Griffin, Cadence Design Systems
Another challenge for SerDes is losses within the channel design. At high speeds, dielectric material can be very lossy, making the appropriate selection of the right material, length, etc., critical for the channel. Many questions about stackup, trace widths, and height from the ground plane need to be defined up front. Simulating a signal with a topology explorer tool extracted from the design can be used to set up and run sweep parameters and push min/max length/spacing values into the Allegro schematic constraint manager (system capture).

Connect the Dots: The ABCs of Clean Schematics

10/19/2022 | Matt Stevenson -- Column: Connect the Dots
The production team is always excited when the first shipment of boards for a new electronic device comes back from the PCB manufacturer. Anticipation builds as the engineer connects the first set of components, puts everything together, and gets ready for that first test. But when something goes wrong—a tiny pop, a sizzle, a puff of smoke or nothing happens at all—the mood can turn from excitement to frustration. Where did the process go wrong? Here, Matt Stevenson provides several commonsense tips for avoiding these types of situations.

Words of Advice: Your Company’s Design Process

05/16/2019 | Andy Shaughnessy, Design007 Magazine
In a recent survey, we asked PCB designers to describe their company’s design process: Is it a rigid workflow they follow to the letter, or a process that allows for their individual techniques? Of course, the comments were illustrative. Only one respondent said, "We just wing it."

Zuken Tempts Engineers with New Year CADSTAR Giveaway

01/13/2016 | Zuken
Zuken is offering electronic engineers who made New Year’s resolutions to try new design software the chance to achieve this now at no cost. The free download of CADSTAR Schematics Design Tool, worth more than $500, will allow the whole design team to instantly explore CADSTAR’s integrated design flow.
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